1. Field of the Invention
Embodiments of the invention relate to fabrication of integrated circuits. More particularly, embodiments of the present invention relate to a process for forming features in a semiconductor substrate.
2. Description of the Related Art
Integrated circuit geometries have dramatically decreased in size since such devices were first introduced several decades ago. Since then, integrated circuits have generally followed the two year/half-size rule (often called Moore's Law), which means that the number of devices on a chip doubles every two years. Today's fabrication facilities are routinely producing devices having 0.13 μm and even 0.1 μm feature sizes, and tomorrow's facilities soon will be producing devices having even smaller feature sizes.
The continued reduction in device geometries has generated a demand for inter layer dielectric films having lower dielectric constant (k) values because the capacitive coupling between adjacent metal lines must be reduced to further reduce the size of devices on integrated circuits. In particular, insulators having low dielectric constants, less than about 4.0, are desirable.
More recently, low dielectric constant organosilicon films having dielectric constants less than about 3.0 have been developed. Extreme low k (ELK) organosilicon films having dielectric constants less than 2.5 have also been developed. One method that has been used to develop low dielectric and extreme low dielectric constant organosilicon films has been to deposit the films from a gas mixture comprising an organosilicon compound and a compound, such as a hydrocarbon, comprising thermally labile species or volatile groups and then post-treat the deposited films to remove the thermally labile species or volatile groups, such as organic groups, from the deposited films. The removal of the thermally labile species or volatile groups from the deposited films creates nanometer-sized voids or pores in the films, which lowers the dielectric constant of the films, as air has a dielectric constant of approximately 1.
Rom Ashing processes to remove photoresists or bottom anti-reflective coatings (BARC) can deplete carbon from the low k films and oxidize the surface of the films. The oxidized surface of the low k films is removed during subsequent wet etch processes and contributes to undercuts and critical dimension (CD) loss.
The porosity of the low dielectric constant films can also result in the penetration of precursors used in the deposition of subsequent layers on the films, such as BARC layers or intermetallic barrier layers (TaN, etc.). The diffusion of barrier layer precursors into the porous low dielectric constant films results in current leakage in a device.
Therefore, there remains a need for a method of processing low dielectric constant films that minimizes damage to the films from subsequent processing steps, such as wet etch processes and the deposition of subsequent layers, such as BARC layers and barrier layers.